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Re:Intel dismisses ‘x86 tax’, sees no future for ARM or any ... by Symmetry on Thursday June 14, 2012 @11:31AM (#4111772)
There is nothing in the instruction set that is more or less energy efficient than any other instruction set

Oh, come on. The problem with x86 is that it's a variable length instruction encoding that isn't self synchronizing. That is, you can start reading at byte 0 and read one set of valid instruction or you can start reading at byte 1 and read another completely different set of valid instructions.

This means that the logic to decode more than one instruction in a clock cycle is really complicated, and complicated means power intensive. For instance, in AMD's Bulldozer chip the instruction decode unit uses more power than the integer execution cluster. Now, ARM has its troubles too (instruction predication on every instruction means another logical dependency, meaning that if you go out of order your scoreboard is more complicated) but they're not as bad and don't really exist in alternate encoding like Thumb2 or the 64 bit one.

Intel is able to compete so well because they tend to have better fabs, they tend to reach a given node like 22nm before everyone else, and their performance on that node tends to be better than other players too. But x86 does have intrinsic disadvantages.

Re:Intel dismisses ‘x86 tax’, sees no future for ARM or any ... by callan on Thursday June 14, 2012 @11:47AM (#4111871)
Disclaimer: I'm a software guy @ Intel.

I feel that a lot of sw folks have a lack of imagination when it comes to hw. A lot of very smart people here work on making an efficient, fast front-end. There's lots of research in this area. To my eyes, the implementations are stunning.

To say that a variable-length CISC instruction set can never be as fast or effecient as ARM is sort-of like saying that an interpreted language can never be as fast as C. And we all know how that goes over on HN.

Re:Intel dismisses ‘x86 tax’, sees no future for ARM or any ... by Symmetry on Thursday June 14, 2012 @12:09PM (#4111999)
I'm sure the front end has had a lot of work and cleverness put into it, and I'm sure that it's able to, say, correctly guess where instruction boundaries are more than 99% of the time without knowing for sure and then remove those instructions from the queue if it turns out that the guess was wrong. But that just means that 4-wide decode is only on the same order of power consumption as execution, instead of being an order of magnitude more like if you'd done thing the naive way. I'm sure that the work they do _is_ stunning, but its work that doesn't even have to be done on more regular instruction sets.

It's not a problem with being variable length or CISC, its a problem with the lack of self-synchronization. If you, say, had 8 or 16 bit blocks were first bit of each block told you whether it was the beginning of an instruction you wouldn't have this problem at all. I'd generally say that for a modern general purpose computer variable length instructions and a large number of op-codes are a good idea, though a large number of addressing modes seems to still be a disadvantage. Its probably no accident that ARM, the "CISCiest" of the RISC processors is so popular right now.

Re:Intel dismisses ‘x86 tax’, sees no future for ARM or any ... by phamilton on Thursday June 14, 2012 @12:11PM (#4112015)
But don't ARM/Marvell/Qualcomm/Nvidia have a lot of smart people working on making an efficient fast front-end?

Overcoming an obstacle is great, but I feel like companies who don't have to overcome that obstacle can focus their energy on other aspects of the product.

Re:Intel dismisses ‘x86 tax’, sees no future for ARM or any ... by Retric on Thursday June 14, 2012 @11:35AM (#4111793)
The relative overhead of x86 vs other instruction set's is meaningless next to intel's current process advantages. ARM is only viable when you have a similar investment in design AND operate on the same manufacturing process.