Standard cells: Looking at individual gates in the Pentium processor

Re:Standard cells: Looking at individual gates in the Pentiu... by morphle on Sunday July 07, 2024 @03:32PM (#40899856)

The best results will be with custom shapes and custom individual placement of every transistor outside standard cell but within the PDK rules. Going outside the PDK rules will be even better but also harder.

The trial and error you do mostly by simulating your transistors which you than validate by making the wafers. You can simulate with mathematical models (for example in SPICE) but you should eventually try to simulate at the molecular, the atom/electron/photon and even at the quantum level, but each finer grained simulation level will take orders of magnitude more compute resources.

Chip quality is indeed limited by the magnitude of computing power and software: to design better (super)computer chips you need supercomputers.

We designed a WSI (wafer scale integration) with a million core processors and terabytes of SRAM on a wafer with 45 trillion transistors that we won't chip into chips. It would cost roughly $20K in mass production and would be the fastest cheapest desktop supercomputer to run my EDA software on so you could design even better transistors for the next step.

We also designed a $800 WSI 180nm version with 16000 cores with the same transitors as the Pentium chip in the RightTo article.

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Re:Standard cells: Looking at individual gates in the Pentiu... by isotypic on Sunday July 07, 2024 @05:04PM (#40900429)

Has this WSI chip been taped out/verified? I must admit I am somewhat skeptical of TBs of SRAM, even at wafer scale integration. What would the power efficiency/cooling look like?

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Re:Standard cells: Looking at individual gates in the Pentiu... by morphle on Sunday July 07, 2024 @05:11PM (#40900459)

The full WSI with 10 billion transistors at 180nm has not been taped out yet, I need $100K investment for that. This has 16K processors and a few megabyte SRAM.

I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects.

The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt.

There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.

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Re:Standard cells: Looking at individual gates in the Pentiu... by initramfs on Monday July 08, 2024 @12:36AM (#40902637)

https://spectrum.ieee.org/1-bit-llm could lower power consumption of data centers.

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Re:Standard cells: Looking at individual gates in the Pentiu... by Robin_Message on Monday July 08, 2024 @08:12AM (#40904682)

This sounds exciting but the enormous and confusing breadth of what your bio says you are working on, and the odd unit errors (lowering "a megawatt" to "2 to 3 terawatt), is really harming you credibility here. Do you have a link to a well-explained example of what you've achieved so far?

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Re:Standard cells: Looking at individual gates in the Pentiu... by actionfromafar on Monday July 08, 2024 @10:00AM (#40905514)

Have to agree. It's fine to have past achievements in the bio I guess but if you are looking for money it doesn't hurt to appear focused.

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Re:Standard cells: Looking at individual gates in the Pentiu... by osnium123 on Monday July 08, 2024 @09:56AM (#40905487)

Are you concerned that going away from standard cells will cause parametric variation, which reduces the value proposition? Have you tested your approach on leading FinFET nodes?

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