From a Raspberry Pi 5: L2 cache line is 128
Vendor ID: ARM
Model name: Cortex-A76
$ lscpu -C
NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE
L1d 64K 256K 4 Data 1 256 64
L1i 64K 256K 4 Instruction 1 256 64
L2 512K 2M 4 Unified 2 1024 128
L3 2M 2M 16 Unified 3 2048 64
Ok, all arm-designed cores for the last 15 years then :)