This describes a timing attack like Spectre/Meltdown on a particular O/S architecture, not all RISC-V cores - looks like there are timing issues with allocation of write port slots when writing to the register file - because division takes so long it's possible to use a late write from division to tell whether a particular speculative branch has been taken or not

There's a CVE table in that article and they seem to have CVEs from a microarchitecture implementing openRISC (entirely different ISA) mixed in there somehow.