If only the the PPC 970 was able to sustain an IPC of eight... it would've been a true miracle to run at 2GHz in 130nm (later 90nm). An IPC of ≥8 for more than a few cycles is something you'll only see during unrealistic micro-benchmarks (e.g. those used to reverse engineer their micro-architecture limits) on the widest of modern out-of-order CPU cores. To really sustain such an IPC in a real-world application workload you still need unusual applications and hardware e.g. a really wide VLIW DSP and *well* *optimised* assembler code.
8 instructions per cycle is a lot, especially on average! I checked and the PPC 970 could fetch, decode, and issue at most 8 ALU ops per cycle, but it could only retire 5 instructions per cycle, so its average IPC is probably less than 4.
Re:X is justifiably slow
by userbinator on Saturday June 01, 2024 @05:21PM
(#40549166)
8 RISC instructions per cycle is much easier to achieve than CISC ones.
For good reason. Clock speed isnt the sole factor in performance. A PowerPC 970 can clock up to 2 GHz, but it only achieves 8 instructions per cycle (on average!) for arithmetic instructions. Modern mobile CPUs clocked at a fraction of 2 GHz achieve much higher throughput for arithmetic. The branch predictor in the PPC chip, while impressive for its time, is simple in comparison to those of modern processors. A CPU without pre-fetching is going to have much worse latency and throughput than any CPU with it. So on, so forth.
Overall, it's naive at best to focus on clock speed for performance. I used to fixate on it when I was a teenager, but not anymore.