Re: point 1, in the 1980 paper, that should be interpreted in the context of the time. Cache memory was still a relatively new idea, and uncommon. Core memory (only supplanted by semiconductor memory c. 1975) had been much slower than digital logic. Core memory was clocked at like 0.1 - 2 MHz when processors were clocked at 1 - 50 MHz. DRAM was faster, up to about 5 MHz by then. And SRAM was very fast; it could be used to construct no-wait-state caches. That had only been used on the largest mainframes in the 60s and early 70s, because it had been prohibitively expensive to construct such cache out of individual flip-flops (the only technology available then).

So, one might say point 1 was so fully true, that it became internalized on chip, and is why we have L1 caches.