Reading Parallel nor Flash with JTAG

Re:Reading Parallel nor Flash with JTAG by monocasa on Monday March 25, 2024 @02:27PM (#39819666)

Yeah, about the only way this would make sense is if they used the boundary scan of the original board's SoC so they didn't have to desolder anything.

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Re:Reading Parallel nor Flash with JTAG by Boardbricker34 on Monday March 25, 2024 @02:58PM (#39820034)

This also does work. Some devices do not have the ability to connect to a part though (no bsdl, no jtag header)

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Re:Reading Parallel nor Flash with JTAG by monocasa on Monday March 25, 2024 @03:27PM (#39820356)

Given that the top bit of every 16bit word looks to be set, I'm not sure that it does work.

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Re:Reading Parallel nor Flash with JTAG by Boardbricker34 on Monday March 25, 2024 @03:57PM (#39820617)

This would work. And I have done this. You need a jtag port and the flash needs to be directly connected to the SOC/MCU/FPGA. This is similar to how EJTAG works but without ejtag, you need to specify the pins themselves. As long as all 16 data and addr pins are connected, this is possible.

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Re:Reading Parallel nor Flash with JTAG by monocasa on Monday March 25, 2024 @04:51PM (#39821125)

I know it can be done. NOR boot flashes like this were typically written and verified via boundary scan at manufacturing time. That's probably how this flash was initially written.

I question whether you successfully performed that operation.

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