It was only faster because of the shorter encoding, something that doesn't matter when the CPU itself is generating the address like on an interrupt. On the 6502, there is a single vector for maskable interrupts, and another for NMI, both of them at the top end of address space.
The 8086/8088 microcode that handled interrupts used a special "segment 0" to provide the address, I don't think it would have been difficult to have some other hardwired value instead of 0. And on later x86 chips there is an actual register for it (IDTR) that can be changed by software - even in real mode, though for reason of backwards compatibility this wasn't usually done.
I don't know if it persisted into 16-bit era CPUs & OSs, but early on the bottom of the memory map was faster to access, so things like interrupt tables¹ were often located there. The 6502 family even had specific load and save instructions for zero-page so not only was the actual operation faster once read & decoded, it took two bytes not three to store so was read faster² and took less space.
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[1] you generally want the response to an interrupt to be as fast as possible, shaving a few clock cycles off could be pretty significant
[2] so a double time saving