You have to be doing pretty strange things with threads, without using mutexes or atomic instructions, to have a problem with this.

RISC-V has a standardised (optional) TSO memory model mode, plus "fence.tso" instruction that works in normal mode, even on CPUs that predate it (it defaults to the stronger "fence rw,rw" in that case). Well, assuming the CPU core designer read the spec carefully and doesn't trap on unknown "fence" instructions (looking at you, THead...)