I was an early user of Verilog at MMI/AMD in 1985-88 and attended the first Verilog user group. The article only mentions TEGAS once, but it was a widely used incumbent and the gate-level descriptions in Verilog matched the TEGAS syntax. See for example https://en.wikipedia.org/wiki/List_of_HDL_simulators

The decision by Synopsys to base their synthesis input on Verilog created an early tipping point to their joint advantage.