Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors
by markhahn on Sunday December 17, 2023 @11:00AM
(#38673698)
well, sorta, since caches are just sram+tag logic. you can parallelize tables, so that each remains fast, but it costs you power/heat. the decoder inherent to sram is what introduces the size-speed tradeoff.
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Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors
by chongli on Sunday December 17, 2023 @11:38AM
(#38673986)
I was ignoring the details on how SRAM works in favour of thinking about it physically. Most of those details just affect the average cell size at the end of the day.
The other physical aspect we’re dealing with is propagation delay and physical distance. That’s where the library analogy really shines: if there’s a minimum size to a book and a minimum size of you (the person doing the research) this corresponds roughly to minimum cell sizes and minimum wire pitch, so you’re ultimately limited in the density you can fit within a given volume.