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A comment on Intel, Samsung, and TSMC Demo 3D-Stacked Transistors. Parent comment

Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors by als0 on Sunday December 17, 2023 @04:29AM (#38671578)
What about if you use register windows or special renaming of architectural registers to internal ones? https://en.wikipedia.org/wiki/Register_window
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Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors by Nevermark on Sunday December 17, 2023 @11:58PM (#38679390)
The amount of stack in the L1 cache is essentially that. A shifting fast access working memory area.

Then think of registers as just part of the fetch & store pipelines for staging operations on stack values.

Forth goes all in with this approach.

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