So do new 8bit processors and almost all processors, x86 cpus still have a reset vector, its 0xFFFFFFF0.
I haven't verified this, but I could see this being used by microcontroller compilers, where address 0x0000 is often a memory-mapped register.
See https://blogs.oracle.com/ksplice/entry/much_ado_about_null_a... and https://blogs.oracle.com/ksplice/entry/much_ado_about_null_e...
(dkersten, I assume you know this, I'm pointing it out for the benefit of others.)
http://lateblt.tripod.com/z80proj1.htm
"What's Happening?
The computer begins with the CPU. When the CPU starts running (which basically happens as soon as it receives power and is reset with the RESET pin), it begins to pull instructions from memory and execute them. Where it starts in memory depends on the individual CPU, but in the case of the Z80, it simply begins at memory address 0, instead of using a reset vector like many other CPUs do. This means that any computer using the Z80 must have a ROM chip at memory address 0 which gives the initial start-up instructions to the Z80."
Also - the memory map during boot time is broadly unrelated to the per-process memory map during OS runtime. Also, if you branch to unexpected memory addresses, you deserve all you get. Also, on a processor with privilege isolation, your ring3 user process can't just cause a reboot.
The CPU doesn't care if the address is all 0s, that's not special to the CPU. So when it turns on it just starts executing at some hard-wired address. That could be 0x0000, 0x8000, or it could be something really random like 0x48C4. Somewhere in the chip's documentation it says what the address is. Once the CPU has power, it loads the first instruction from that address, and then it executes everything as normal.
So you wire up the computer so that some little piece of ROM (for example the BIOS) sits at that address. When the chip turns on, you know what instructions it will start executing.
Once things are going, you could set things up to be more complicated (such toggling pins to signal the ROM chip to stop listening so you could map normal RAM into that address), but that's the basic idea.
(Unless you get lucky, and it's a branch-predict, that turns out to be an incorrect predict, and then flushes and re-branches into valid memory...)
If you arrange matters so that until the CPU tells you differently, memory address 0x0000 holds your firmware, then all can proceed from there.