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Re:Major Changes at RISC-V Designer SiFive by Joker_vD on Tuesday October 24, 2023 @12:30PM (#38001534)
How do you even use all those registers? Serious question. I've toyed with a couple of 256-register ISAs, and the moment you hit function calls/parameter passing you realize that to utilize those efficiently, you really need some way to indirectly refer to registers, be it register windows, or MMIX's register slide, or Am29k's IPA/IPB/IPC registers; the only other option seems to be to perform global register allocation but that hardly works in scenarios with separate compilation/dynamic code loading.
Re:Major Changes at RISC-V Designer SiFive by benj111 on Tuesday October 24, 2023 @12:52PM (#38001842)
Off the top of my head I don't really know. But then if you had asked me 20 years ago if we'd need multi core multi GHz multi GB computers to display a web page I'd probably have said no.

I suppose the os could reserve registers for itself to save swapping in and out quite so often.

Register windows for applications/functions/threads.

Or maybe something radically different, like get rid of the stack, and treat them conceptually like a list?

Re:Major Changes at RISC-V Designer SiFive by _a_a_a_ on Tuesday October 24, 2023 @03:48PM (#38004410)
> I've toyed with a couple of 256-register ISAs, and the moment you hit function calls/parameter passing you realize that to utilize those efficiently

Very revealing, thanks, this had never occurred to me