Major Changes at RISC-V Designer SiFive

Re:Major Changes at RISC-V Designer SiFive by Symmetry on Tuesday October 24, 2023 @11:53AM (#38000926)

Once you're moving to alignment within a larger fixed width block you don't even need to stick to byte boundaries. I've got a toy ISA I've played around with that breaks 64 bit chunks into a 62 bit instruction, a 40 and a 21 bit instruction, or 3 21 bit instructions.

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Re:Major Changes at RISC-V Designer SiFive by leosarev on Tuesday October 24, 2023 @03:41PM (#38004317)

I think Itanium did something like that

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Re:Major Changes at RISC-V Designer SiFive by Symmetry on Tuesday October 24, 2023 @03:55PM (#38004511)

Yup, 128 bit bundles with 3 instructions each, and ways to indicate that different bundles could execute in parallel.

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