Re:Major Changes at RISC-V Designer SiFive
by ribit on Tuesday October 24, 2023 @11:58AM
(#38001027)
Yes, x86 works, but appears to pay a huge cost in power consumption to squeeze out those last few % of performance. Whether it’s just the property of how the mainstream x86 implementations have grown historically or the ISA itself remains to be seen.
I also agree that RISC-V decoders are simpler but only because the base ISA itself is very limited. Once you add functionality like FP, atomics, Zb extension, vectors etc… there is not that much difference. And the need to do fusion for address computation adds another layer of complexity on top.
Re:Major Changes at RISC-V Designer SiFive
by hajile on Tuesday October 24, 2023 @12:25PM
(#38001457)
RISC-V already has those things and the answer seems pretty clear. P670 gets around the same performance as A78 while being 50% smaller (according to SiFive) while having vectors, atomics, floats, etc.
Re:Major Changes at RISC-V Designer SiFive
by hardware2win on Wednesday October 25, 2023 @09:07AM
(#38012377)
>Yes, x86 works, but appears to pay a huge cost in power consumption to squeeze out those last few % of performance. Whether it’s just the property of how the mainstream x86 implementations have grown historically or the ISA itself remains to be seen.
https://chipsandcheese.com/2021/07/13/arm-or-x86-isa-doesnt-...
RISC-V compressed instructions are provably WAY less complex to decode than x86 and only a bit more complex than ARM64. Once you get past slicing apart the instructions, RISC-V decoders are much more simple than ARM64 because the stuff they are decoding is way less complex.