Really, by a reasonable definition CISC was dead long before x86 became a thing. We don't even conceive of architectures where every instruction has 6 operands, including double indirection and implicit increments.
Re:Major Changes at RISC-V Designer SiFive
by Pet_Ant on Tuesday October 24, 2023 @03:37PM
(#38004255)
> We don't even conceive of architectures where every instruction has 6 operands, including double indirection and implicit increments.
Is this an exaggeration, or were there ever such ISAs?
It's a half-remembered description of VAX, but it's not much of an exaggeration if at all.
Re:Major Changes at RISC-V Designer SiFive
by Pet_Ant on Wednesday October 25, 2023 @10:19AM
(#38013103)
For those curious, I found this VAX manual, but haven't found anything truly egregious yet:
Re:Major Changes at RISC-V Designer SiFive
by brucehoult on Sunday October 29, 2023 @06:11PM
(#38063365)
MOVC6
Yeah I'd tend to agree, in particular x86 variable length encoding is a lot more complex than the RISC-V encoding!
What I'm really getting at is CISC and RISC aren't well-defined things and it's interesting seeing how the design of RISC-V is getting pulled in different directions.
> so at least on RV32 it is very light weight, and it adds barely any logic to a core. It's almost always worth it to turn on C extensions versus making the cache bigger or trying to speed up main memory.
Definitely, and the Qualcomm proposals are that things should stay that way for RV32/low end in general. It's high-end RV64 they care about.
> On the other hand, I suppose if you are already committed to deep speculation and out of order, compressed instructions might extract a disproportionate cost, maybe less so in decode and more so in precise exception handling and in tricks like register renaming.
This is the root of it. It's easy enough to do a study demonstrating changes in static code size, also easy enough to build a low-end RISC-V processor and examine the trade-offs. It's all a lot more complex at the higher-end especially as high-end RISC-V cores are far from mature.