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A comment on Major Changes at RISC-V Designer SiFive. Parent comment

Re:Major Changes at RISC-V Designer SiFive by rsaxvc on Tuesday October 24, 2023 @08:31AM (#37998201)
> I think an example is something like opcodes crossing I-cache lines

Consider also a 16-bit aligned 32-bit instruction crossing a page boundary, potentially with different access permissions. This type of bug allowed userspace applications to hang early Cortex-A8 based phones(ARM errata 657417).

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Re:Major Changes at RISC-V Designer SiFive by rsaxvc on Wednesday October 25, 2023 @05:05PM (#38018365)
See also: Intel SKX102, whose documentation has nice diagrams.
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