News for hackers. Stuff that matters.
Re:Major Changes at RISC-V Designer SiFive by jstanley on Tuesday October 24, 2023 @07:16AM (#37997409)
> instructions will frequently need to be reordered to align

Can't you pad it with nops up to the alignment boundary?

Even if there's not an explicit nop instruction in 16-bit and 32-bit variants (I don't know) there's surely something you can find that will have no side effects.

Re:Major Changes at RISC-V Designer SiFive by londons_explore on Tuesday October 24, 2023 @07:25AM (#37997492)
Yes, of course - but in general you want to avoid padding with nops because it makes the code larger (which, as well as costing more RAM, also uses more power and time to read the code from RAM, and fits less code into the instruction cache, which makes the power and time cost of reading code from RAM even bigger).

If you can make a compiler fill those NOP slots with useful instructions, then all the better.

It adds complexity for humans writing assembly code by hand, but that is a tiny minority of code now.

Re:Major Changes at RISC-V Designer SiFive by KMag on Tuesday October 24, 2023 @10:00AM (#37999296)
For one, I don't see why you would ever pad a 16-bit instruction with a 16-bit noop instead of just using the 32-bit equivalent instruction. That way, you can skip decoding the no-op.
Re:Major Changes at RISC-V Designer SiFive by StillBored on Tuesday October 24, 2023 @11:47AM (#38000821)
Because you have a long odd numbered chain of 16-bit ops. Ex: 15 16-bit ops, leaves you with a 16bit NOP in order to realign for the following 32-bit op.
Re:Major Changes at RISC-V Designer SiFive by Joker_vD on Tuesday October 24, 2023 @12:14PM (#38001286)
Use 14 16-bit ops instead, and use a regular 32-bit op as the 15th instruction (which is already correctly aligned since 14 is an even number).
Re:Major Changes at RISC-V Designer SiFive by KMag on Tuesday October 24, 2023 @08:21PM (#38007597)
To be more clear: if a 16-bit instruction is 32-bit aligned, then you might want a 16-bit noop so that the instruction following the noop is also 32-bit aligned. But, in that case, you could just use a 32-bit aligned 32-bit instruction at the same location. No padding, one instruction saved, and the following instruction is still 32-bit aligned.

If the 16-bit instruction isn't 32-bit aligned, then the following instruction will be 32-bit aligned with no padding.

So, the question is equivalently: "Why would you ever want to add padding after a 16-bit instruction in order to force the next instruction to not be 32-bit aligned?"