An ETH Zurich team have done a triple core lockstep version for cubesats: https://www.theregister.com/2023/10/05/riscv_microcontroller...
Gaisler is also current one of the biggest players there IIRC. I've used them for stuff in the past.
That remark sounds like the pot calling the kettle black. Two wrongs don't make a right you know.
I believe this is because ARM wasn't confident they'd be able to enforce licensing effectively.
For non-FPGA designs, they only need to have insider knowledge from a handful of fab companies to detect those using cores without valid licenses.
How exactly ARM does this isn't always clear. For hard IP there is a GDS layer called IP tags and the foundry is supposed to scan this layer and can report numbers back to IP providers like ARM, Cadence, Synopsys, etc. If the customer removed this layer "accidentally" then the foundry can still scan for certain patterns and structures within the GDS mask data. Like a unique hidden watermark and report back to the IP vendor.
For soft IP that is synthesized there are probably other ways to do it but I'm not that up to date.
There are companies that take commercial parts and nuke them under a beam at places like TAMU to profile their performance then resell to aerospace. The issue is by the time this flight qualification happens the parts are old as hell.
There are the famous "old as hell" rad-hard powerPCs which cost $200k, used for historical reasons or extreme environments like a fly-by of Venus. It's true that older chips may be inherently more radiation tolerant due to larger features on the silicon but it's a misconception that CPUs used in space are therefore always old as hell. These are usually selected because they are good enough and to reuse design and qualification from a previous project instead of spending millions and ten person-years on a new design.
But commercial spacecraft these days usually use something like this[1] triple-redundant 50MHz softcpu implemented on an FPGA or this[2] Ultrascale ~1Ghz SOC protected by a secret sauce of separate FPGA for watchdog and overcurrent detection. Both are modern, run linux and use modern development environments/tools. The former is slower but can recover upsets in realtime, while the latter is much faster but needs to reset itself to recover at least some types of upsets.
[1] https://www.aac-clyde.space/wp-content/uploads/2021/10/AAC_D...