On a certain level this is like arguing that you will never see this problem in an Arduino.

I mean, sure. On many levels and planes you are correct, but not where any of the intersections matter.

If it's not clear enough, I am not talking whatever Arduino strawman you came up with.

I am talking about RISC architectures such as RISC-V (which I mentioned by name), the sort that can scale all the way up to supercomputers and down to microcontrollers.

There is no justification for putting up with x86's complexity. This complexity has negative consequences such as vastly increased likeliness of micro-architectural bugs.

It is utter madness for many of its current popular uses, such as in servers handling personal data.

I see you’re basically trying to “No True Scotsman” a definition where anything which isn’t RISC-V is too complicated. That’s a shame as the time you’re spending on counterproductive RISC-V advocacy could have been spent learning about this class of attack and how it has nothing to do with the ISA.

When a CPU implements speculative execution, this class of attack becomes a concern. If it doesn’t, it’ll be too slow for most applications. Fortunately, the people who are - unlike you - actually helping RISC-V are working on efficient countermeasures:

https://arxiv.org/abs/2206.04507