While it is not strictly necessary in all scenarios, I think you will just not be able to get efficient circuits if you do not have a sense of what type of logic your verilog code snippets map to.

I honestly believe that if you do not understand at least some basics, things will be way more painful and opaque than necessary, so it is a no-brainer IMO.

You also do not need to have an FPGA to learn this stuff.