A Single-Cycle 64-Bit RISC-V Register File

Re:A Single-Cycle 64-Bit RISC-V Register File by hasheddan on Friday August 04, 2023 @12:20PM (#37002102)

Author here -- thanks for the feedback! This is a quick post that is focused on how to logically think about the circuit, but I agree that all of the attributes you enumerated are valuable information as well. I plan to continue diving deeper in future posts. I am currently posting every Friday as part of my goal of gaining a deep understanding of chip design[0]. Please feel free to continue to provide feedback on future posts as well!

[0]: https://danielmangum.com/posts/a-three-year-bet-on-chip-desi...

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Re:A Single-Cycle 64-Bit RISC-V Register File by boesboes on Friday August 04, 2023 @12:38PM (#37002371)

I liked the post. as a novice with fpgas and hdls, I find posts like this very approachable. Refreshing tbh

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Re:A Single-Cycle 64-Bit RISC-V Register File by therealcamino on Friday August 04, 2023 @12:28PM (#37002230)

I think the article is fine but what you're really driving towards is the idea of synchronous design, and how that simplifies design and analysis. Some of the objections here might go away if it were framed that way.

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Re:A Single-Cycle 64-Bit RISC-V Register File by hasheddan on Friday August 04, 2023 @12:31PM (#37002272)

That's a great point. Thanks for the feedback!

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Re:A Single-Cycle 64-Bit RISC-V Register File by perfopt on Saturday August 05, 2023 @09:27AM (#37011816)

Perhaps showing the synthesized gates and how say a structural version of the code will synthesize would explain in more detail

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