Re:Intel AVX10: The Successor to AVX-512
by adrian_b on Monday July 24, 2023 @08:09PM
(#36855999)
Actually on Zen 4 using 512-bit instructions instead of 256-bit instructions frequently improves the performance a lot, despite using the same execution units.
The reason is that in Zen 4 the relatively narrow instruction decoder is frequently the bottleneck, so twice less instructions can influence the speed very much.
On future CPUs that will be able to decode more instructions in parallel, like Zen 5 and the future Intel CPUs, 512-bit instructions might no longer increase the speed when the width of the execution units remains of 256 bits, so perhaps even AMD may introduce a split between laptop CPUs that implement only the 256-bit subset of AVX-512 rebranded AVX10 and server CPUs that implement the full AVX-512 a.k.a. AVX10.
The reason is that in Zen 4 the relatively narrow instruction decoder is frequently the bottleneck, so twice less instructions can influence the speed very much.
On future CPUs that will be able to decode more instructions in parallel, like Zen 5 and the future Intel CPUs, 512-bit instructions might no longer increase the speed when the width of the execution units remains of 256 bits, so perhaps even AMD may introduce a split between laptop CPUs that implement only the 256-bit subset of AVX-512 rebranded AVX10 and server CPUs that implement the full AVX-512 a.k.a. AVX10.