AMD Zen4 has 256-bit load/store to L1 cache, which means it'd take a load/store unit 2-clock ticks to execute any 512-bit load or store. (Though Zen4 has multiple load/store units, so maybe its not that big of a deal in practice).
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GPUs are 32-wide with 32-bits each, or 1024-wide operations in practice. GCN was 64-wide with 32-bits each or 2048 wide in practice.
The reason why AVX512 was a big deal isn't the width btw. But instead the design of the instruction set. AVX512 is the most advanced CPU vector instruction set ever made, with huge inspirations from NVidia's PTX or AMD's GCN.
Of course, GPU-assembly remains superior. I don't think that RISC-V (or whoever) should be copying AVX512 or even AVX10, they should be looking at NVidia PTX or NVidia SASS as inspiration.
Can you explain what makes it the above? I haven't really worked with avx512 before, only up to avx2 and rvv.
2. AVX512 has vgather and vscatter, aka vector-load and vector-store. While no computer accelerates this process, this still simplifies programming and read/writes to memory can be thought of on a per-lane basis.
3. Compress and Expand, new instructions not found in GPU-space, perform the stream-compression operation (and inverse operation). See: https://www.cse.chalmers.se/~uffe/streamcompaction.pdf , lots of practical applications here, nice to see just a simple "instruction" that handles this detail. Though GPU programmers can prefix-sum and build this primitive themselves in practice, its a common enough operation that a proper-instruction is likely a good idea.
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Just a few tidbits of AVX512 ISA that shows that Intel really knows what they're doing here.
#1 can be seen as a 64-bit generalization to the cmov conditional instructions that are in Intel's normal 64-bit instruction set. Except instead of being a "1-bit" compare or 1-bit if-statement, might as well generalize it to a 64-bit operation across 64x8-bit bytes that naturally map into a 512-bit register, right?