Extension in this context basically just means new registers/instructions that didn't exist on a 386. Even floating point support on x86 is technically an extension. SSE (which adds the xmm registers) has existed on all x86 CPUs made by Intel in the last 20+ years, and the ymm registers/instructions are part of AVX2 which has existed on all x86 CPUs made by Intel in the last 10+ years.
Re:Intel AVX10: The Successor to AVX-512
by Am4TIfIsER0ppos on Tuesday July 25, 2023 @05:25AM
(#36859910)
I don't mean mmx through avx2 when I said extensions. I mean the "vector length" extensions/flag for avx512 that lets you know you can use those instructions with xmm and ymm sized operands. Since it is a flag it means it is a theoretical optional feature whereas it should have just been part of the avx512 base. With the hindsight of what Intel want for avx10 there should have been flags for xmm, ymm, and zmm operands. That would be excellent for the "E" cores.
> being able to work for both P and E cores
Oh yes I forgot they were gimping their own processors.
> the converged version has a maximum vector length of 256-bits [on] the E cores while P cores will have optional 512-bit vector use
Maybe they shouldn't have made xmm and ymm "extensions" to the base set to begin with.