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A comment on Ask HN: How to start a fabless chip company targeting a modern process node?. Parent comment

Re:Ask HN: How to start a fabless chip company targeting a m... by tiberious726 on Tuesday July 11, 2023 @01:51AM (#36676881)
No offense intended, but either you don't have a firm conception of just what FPGAs/ASICs are, or this is actually truly revolutionary. Built it in a simulator and see what the performance numbers are. Even talking to TSMC/Intel/Samsung is a post-funding thing, which your shouldn't have any problem raising if it actually works (Hell, DM me if you actually prove it, I'd go in).
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Re:Ask HN: How to start a fabless chip company targeting a m... by chromoblob on Tuesday July 11, 2023 @03:55AM (#36677785)
My problem is I don't know how to simulate without concrete PDK data and get useful numbers. My prototype design will be lost, unguided.

DM to where?

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Re:Ask HN: How to start a fabless chip company targeting a m... by tiberious726 on Thursday July 13, 2023 @12:57PM (#36712380)
Lol, fair point, username at gmail

Why do think your architecture needs pdk information? You should be able to show a _massive_ improvement at the logic gate level, then get funding to hire a security team which would let you pass the fabs audits

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Re:Ask HN: How to start a fabless chip company targeting a m... by chromoblob on Saturday July 15, 2023 @11:50AM (#36737943)
Gate-level model is meaningless for measuring performance without parameters outside of the model.

If I make only a gate-level model, I have no idea how to prove the benefit of my design, short of just showing it in entirety.

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