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A comment on The legend of “x86 CPUs decode instructions into RISC form internally”. Parent comment

Re:The legend of “x86 CPUs decode instructions into RISC for... by hinkley on Sunday June 18, 2023 @02:05PM (#36382666)
We had to touch MIPS in school. Having to deal with branch delay slots was cruel. It broke some of my classmates. We were on a cusp of needing every programmer we could get and they were torturing students. I hope those teachers lost sleep over that.

Am I correct in recalling they removed branch delay slots in a later iteration of the chips?

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Re:The legend of “x86 CPUs decode instructions into RISC for... by IAmLiterallyAB on Sunday June 18, 2023 @05:33PM (#36384734)
IIRC They made new branch instructions without delay slots, but the normal branch instructions still have delay slots.

Had to write MIPS assembly by hand recently, incredibly counter intuitive.

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