As far as I know, Apple has the NAND controller integrated into the SoC. The NAND controller needs to have ECC to keep the error rates on flash down to something acceptable.

That was sort of what I was wondering, if the NAND controller has some extra Apple Stuff(tm) beyond standard ECC.

I'm pretty sure that is the reason why support for Fusion Drives was abruptly ganked and punted out by a year.

The standard for SSDs goes far beyond the ECC used on DRAM. Every SSD controller designer will have their own proprietary scheme, often a simple and fast BCH that falls back on LDPC for higher error rates. The exact codeword sizes and other parameters of the codes are vendor-specific.