Cache protocols usually have at least some optimisation for getting the accessed bytes first, which isn't normally present in a protocol designed to exchange packets. What I mean by that is that if your CPU reads byte 27 of a 32byte cache line, the cache is going to read 32 bytes from memory but it will start at byte 27 (or more likely bytes 24..27) so that it can unblock the CPU as fast as possible. I'm not actually sure if that makes its way down to the multicore coherency protocols - if the buses are sufficiently wide maybe they don't bother - but it's seems plausible.