Open-source high-performance RISC-V processor

Re:Open-source high-performance RISC-V processor by rapiz on Sunday March 26, 2023 @07:35AM (#35313347)

It's actually chisel. But github marks it as scala because chisel is based on scala.

Other HDL based on scala includes SpinalHDL.

These two HDL are pretty welcomed because of opensource and usability. You can find lots of projects in them. Notably rocket-chip, which is also in chisel. https://github.com/chipsalliance/rocket-chip

They're around for a while but still young and some people are pushing for adoption.

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Re:Open-source high-performance RISC-V processor by monocasa on Sunday March 26, 2023 @08:19AM (#35313675)

It is scala. Chisel is just a scala framework. Conceptually it's not quite an HDL but instead a scala program that metaprograms the actual RTL netlist. So there's no chisel compiler other than the standard one that comes with sbt; you then run the resulting chisel program on your computer to generate the netlist.

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Re:Open-source high-performance RISC-V processor by phendrenad2 on Sunday March 26, 2023 @12:08PM (#35316043)

It's scala + a DSL called "chisel" that you write by chaining scala keywords and symbols in the right order.

There, solved it once and for all. :)

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Re:Open-source high-performance RISC-V processor by georgelyon on Sunday March 26, 2023 @12:13PM (#35316109)

This is not strictly true anymore as the low-level (FIRRTL) compilation is powered by CIRCT (http://GitHub.com/llvm/circt) which is built using MLIR (part of the LLVM project: https://GitHub.com/llvm/llvm-project)

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