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A comment on Verilog Ethernet: Work-in-Progress 100BASE-TX PHY. Parent comment

Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY by knorker on Saturday March 18, 2023 @05:36AM (#35207600)
A distinction without a difference for the problem with AGPL.
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Re:Verilog Ethernet: Work-in-Progress 100BASE-TX PHY by pabs3 on Sunday March 19, 2023 @03:27AM (#35216817)
Sure, just correcting a factual issue in your comment.

Edit: although, I disagree AGPL is problematic, see my other comment.

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