RISC-V Business: Testing StarFive's VisionFive 2 SBC

Re:RISC-V Business: Testing StarFive's VisionFive 2 SBC by thomashabets2 on Friday March 03, 2023 @06:42PM (#35016508)

I wonder how much of the performance will improve when compilers get better at RISC-V.

It's been a long time since I could beat the compiler at optimizing assembly on x86, yet in the end merely unrolling a loop and keeping an eye on write-read stalls I managed to get a simple "multiply array by const" about 56% less time (more than twice as fast):

https://github.com/gnuradio/volk/pull/619

And that's with hardware that doesn't even have vector instructions! I'd understand GCC not supporting that yet.

Some other quickstart docs and hot takes from me on this hardware: https://blog.habets.se/2023/01/VisionFive-2-quickstart.html

Edit: Oh yeah, if you can decipher my tables then you can compare some performance ray tracing with pov-ray here: https://qpov.retrofitta.se/stats

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Re:RISC-V Business: Testing StarFive's VisionFive 2 SBC by snvzz on Friday March 03, 2023 @08:07PM (#35017089)

>(link) It doesn’t have AES instructions, so be deliberate in how you compare this benchmark to anything, but here’s openssl speed:

Beware the CPU does not have the scalar or vector cryptographic extensions, but the SoC has a cryptography acceleration module.

It is not supported in the current image's kernel, but the patch to support it is being reviewed upstream for merging.

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