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A comment on RISC-V Business: Testing StarFive's VisionFive 2 SBC. Parent comment

Re:RISC-V Business: Testing StarFive's VisionFive 2 SBC by jburgess777 on Friday March 03, 2023 @03:10PM (#35014407)
The repo below has support for building a 32bit RISC-V CPU for de10nano. It also includes information about booting Linux.

https://github.com/litex-hub/linux-on-litex-vexriscv

The CPU will likely have a clock speed around 100Mhz, far slower than the 1.5Ghz 64bit cores on the VisionFive 2 or Pi4. The FPGA might still be useful if you want to customize the CPU or integrate other custom hardware.

[ Parent | on HN ]
Re:RISC-V Business: Testing StarFive's VisionFive 2 SBC by whitehexagon on Saturday March 04, 2023 @04:07AM (#35019421)
Open source tool chain and open source cores, wow, nice progress since I last looked into this.
[ Parent | on HN ]