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A comment on AMD ymm registers are rolling back. Parent comment

Re:AMD ymm registers are rolling back by Const-me on Wednesday March 01, 2023 @08:01AM (#34981875)
Micro-ops aren’t simpler than the AMD64 instructions, the complexity is about the same. For instance, the following instruction

    vfmadd231ps     ymm3, ymm1, YMMWORD PTR [rax-256]
does quite a few things (memory load, and 8-wide fused multiply+accumulate), yet it decodes into a single micro-op.

Most AMD64 instructions decode into a single micro-op. Moreover, there’s a thing called “macro-ops fusion”, when two AMD64 instructions are fused into a single micro-op. For example, scalar comparison + conditional jump instructions are typically fused when decoding.

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Re:AMD ymm registers are rolling back by mort96 on Wednesday March 01, 2023 @10:21AM (#34983322)
That's an important detail, not all macro-ops are more complex than micro-ops, and most of our everyday x86 instructions are simpler than the more complex micro-ops.

But we can agree that the complexity ceiling is much higher on macro-ops than micro-ops, right? The µop you mentioned does one (vector) FMA operation on two (vector) registers and stores the result to RAM. While in x86, we have things like the rep instruction which repeats an action until ECX is zero, or the ENTER and LEAVE instructions to set up and tear down a stack frame. Those are undoubtedly implemented in terms of lots of micro-ops.

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Re:AMD ymm registers are rolling back by Const-me on Thursday March 02, 2023 @03:02AM (#34993252)
> complexity ceiling is much higher on macro-ops than micro-ops, right?

Other examples are crc32, sha1rnds4, aesdec, aeskeygenassist - the math they do is rather complicated, yet on modern CPUs they are single micro-op each.

> one (vector) FMA operation on two (vector) registers and stores the result to RAM.

It loads from there.

> Those are undoubtedly implemented in terms of lots of micro-ops.

Indeed, but I don't think it's complexity. I think they use microcode for 2 things: instructions which load or store more than 1 value (a value is up to 32 bytes on AVX, 64 bytes on AVX512 processors), or rarely used instructions.

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