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A comment on AMD ymm registers are rolling back. Parent comment

Re:AMD ymm registers are rolling back by psychphysic on Wednesday March 01, 2023 @07:53AM (#34981809)
Macro op fusion is more what I had in mind when I called it JIT and not interpretation.

Not sure what the distinction is but that's where it is to my mind

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Re:AMD ymm registers are rolling back by yvdriess on Wednesday March 01, 2023 @11:51AM (#34984586)
It's true that the distinction is a bit vague, the term JIT is overloaded to enough that it stopped being a useful technical term.

Compared to 'JVM JIT' or 'LuaJIT': there is no instrumentation to detect what is hot or not. The CPU frontend will crack x86 instructions into micro-ops, while looking for some patterns to merge certain instructions or uops into larger micro-ops. The micro-coded instructions (like many of the legacy instructions) are likely just lookups.

Most of this is my speculation, mind. Modern CPU frontends are still kind of a black magic box to me, but I think they are limited by relatively simple transformations by virtue of being on the critical execution path.

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Re:AMD ymm registers are rolling back by to11mtm on Wednesday March 01, 2023 @12:59PM (#34985799)
There is a Micro-op cache in play in many cases like Zen [0], but I'm not entirely sure what it does.

[0] - https://chipsandcheese.com/2022/11/05/amds-zen-4-part-1-fron...

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Re:AMD ymm registers are rolling back by AstralStorm on Thursday March 02, 2023 @05:34AM (#34994186)
Micro-op cache is literally L1 cache after the instructions are broken into micro-ops.

It's not a magic arc profiling optimization either.

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