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A comment on “Clean” Code, Horrible Performance. Parent comment

Re:“Clean” Code, Horrible Performance by sgarland on Wednesday March 01, 2023 @06:37AM (#34981223)
> Two cpu generations later, the Pentium comes out, and both mul and div take 1 clock cycle.

Where are you getting this information? Agner[0] lists DIV as taking 17 cycles at best (8-bit operand already in a register) on the P5, and MUL as taking 11 cycles. Even Tiger Lake takes 6 cycles for DIV.

There are ways [1] to beat that, but I don't think you can get it down to a single cycle.

[0]: https://www.agner.org/optimize/instruction_tables.pdf p.162

[1]: https://lemire.me/blog/2019/02/08/faster-remainders-when-the...

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Re:“Clean” Code, Horrible Performance by aforwardslash on Wednesday March 01, 2023 @01:28PM (#34986330)
You are completely right, I just had a major brain fart. I probably mixed up some things (or had some bad/incomplete source at the time). More than two decades have passed, so its probably me with wires crossed.
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