Typically, sram (cache memories for example) doesn't scale as much as core logic, and interconnect (connections between the cores, DDR, etc...) almost don't scale at all.

This is highly dependent on the design of the SoC, but the core logic is rarely the largest of the three, so you will not see a 35% reduction of the total area of the chip: only of the areas the most densely packed with logic. What you could have for example is a 35% more powerful neural network accelerator in the same area as the previous generation. But you will not have 35% bigger cache.