How many threads would it take to hide 100ns of DRAM access latency and what serial performance would we get?
It doesn't have to be hidden completely, there are still caches.
With 2 unstalled threads you effectively halve it (in terms of throughput), 4 unstalled threads you effectively quarter it, etc.
On x86 SMT gets a bad rap because its never been tremendously effective. It's much more effective in IBM's implementation on Power. It wouldn't be hard to imagine some Itanium SMT monster.