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A comment on Intel discontinues pathfinder for RISC-V program. Parent comment

Re:Intel discontinues pathfinder for RISC-V program by colejohnson66 on Friday January 27, 2023 @02:52PM (#34550878)
Despite outward appearances, AVX-512 follows two paths: server and consumer. Each year, the support on one tier is larger than before (until Alder Lake, that is). The various "sub instruction sets" are more for categorization reasons than differences in capability.

If you look at AVX-512's chart on Wikipedia[0], but reorder it into (the discontinued) Xeon Phi, server, and consumer tiers, it's a nice chart showing increasing support as time goes on. For example, -ER, -PF, -4FMAPS, and -4VNNIW weren't really "removed" after Xeon Phi because the server and consumer lines never had them. That chart is just horrible because it tries to show a timeline without clarifying the differences in tiers.

[0]: https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512

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Re:Intel discontinues pathfinder for RISC-V program by adgjlsfhk1 on Friday January 27, 2023 @04:05PM (#34551850)
there still is the fundamental problem that most people who do compiler work mostly don't work on servers so Intel's strategy has kept avx 512 from having good support
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Re:Intel discontinues pathfinder for RISC-V program by imtringued on Saturday January 28, 2023 @10:09AM (#34558120)
I think the biggest issue is that auto vectorization would need a programming language that is designed around it.

Vectorization is a niche but GPU programming isn't (shader programming is very popular).

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Re:Intel discontinues pathfinder for RISC-V program by CoastalCoder on Monday January 30, 2023 @01:24AM (#34576459)
> I think the biggest issue is that auto vectorization would need a programming language that is designed around it.

I don't think that's correct.

The compilers I work with do a pretty decent job of auto-vectorizing the inner-most loops of an algorithm, especially if they know the loop bounds at compile-time.

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