> The big-little architecture is built around the idea of large cores idling / shut down most of the time, and only waking up to serve a peak load

This would suggest placing E cores between (or even inside) P cores, every cluster of them maybe on a small chiplet.

I wonder if the idea could go as far as having efficient and performant execution units in the same processor, with the reorder buffer issuing instructions to different units according to how far down the instruction stream the result is needed.