5nm is extremely inefficient to make: IIRC, you need to submerge the parts in ultra-pure water and blast it with a ultraviolet laser to get down to 5nm. This is because even ultra-pure filtered air has too many particles that disperses the laser that you're off by a few nanometers... ruining the design. Filtering all that water and powering ultraviolet-spectrum lasers is extremely high power / electricity usage.
In contrast, a 40nm process is still airborne. You can largely do 40nm with "more standard" equipment. No ultra-pure water needed. No ultraviolet lasers. No quad-patterning. You can use "regular" light, with "regular cleanroom air", and "regular" processes to make the design at far, far lower costs (or at least, with less electricity).
---------
IIRC, the "ideal" cost-efficiency moving forward is to rebuild our older fabs for 300mm wafers, standardize upon that wafer size. Older fabs were standardized on smaller 200mm wafers with only ~45% area of the bigger wafers (and less in practice, because the edge of a wafer has all sorts of inefficient issues involved).
There's also the issue that a lot of these designs, such as Power MOSFETs, are... just one, maybe two, transistors. If your transistor is like a centimeter in size, there's no point using 5nm or 40nm or even 90nm nodes on it. There's just much much cheaper ways to fabricate a "centimeter-sized" MOSFET. There's all sorts of application of "chips", from 1-transistor Power MOSFETs to ~100 transistor op-amps, to ~10,000 transistor transceivers, to 10-million+ transistor NAND-Flash arrays. (1 Megabyte isn't much these days though, lol)
5nm is a multi-billion dollar fab, absurdly high running costs, and very expensive wafers.
As a data point: 5nm lithography equipment is > $100M/unit, needs megawatts of power to run, and they handle about 60-80 wafers per hour.
90nm lithography equipment is ~ $1M/unit, needs kilowatts of power to run, and they handle about 60-80 wafers per hour.
So a wafer scanned on 5nm equipment that could have been scanned on 9nm equipment is carrying a very large capital and operational cost burden that's pointless.
Is it possible to make bigger transistors using a smaller process? Just because you are using saying a 7nm process, can't you still make a transistor (like if you needed) that was the same size as it was on 90nm? I think of newer processes as merely being more precise so you could still do the old designs on them, you are just unecessarily tying up the newer machines... but concievably in the future you could just start using 5nm process to keep producing 30 nm and 90 nm chips just to consolidate production lines, non?
I know nothing about this, so I'm just asking.