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Re:IEDM 2022: Did We Just Witness the Death of SRAM? by vlovich123 on Thursday December 15, 2022 @04:08AM (#33996999)
I wonder if we’ll have smarter cache eviction strategies. For example, when there’s a context switch we pollute the cache and it takes time for it to ramp up. I wonder what it would look like if the cache for each context was fully flushed out (modulo addresses marked as shared across processes), particularly on a kernel switch (not to RAM for perf reason but maybe to a much larger L4 cache or at a minimum the L1/L2 caches could be context swapped). That would make the existing cache far more efficient. Similarly, what if some data could be marked as “infrequently used” and using a different cache slab. An example of that might be when the OS is compressing unused pages - it’s better to use a separate cache space for things like that to avoid evicting the useful stuff.

Similarly, what would it look like if we dedicated CPU cores to running the kernel and other cores executed the kernel through io_uring and futexes only. That could significantly reduce cache pollution although there may be more cross cpu cache shoot down?

Just for context, most L3 caches today are the size of the entire RAM from 20 years ago. You’d think that you should be able to run the hyper visor totally out of L3 cache.

Also some of these alternate architecture would also be inherently more secure because it would be harder to exploit side channel attacks across contexts.

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