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A comment on SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds for HPC. Parent comment

Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by kstrauser on Monday December 12, 2022 @03:24PM (#33959745)
Ah, thank you for that! So you could fetch 1/(60ns) bytes per second synchronously, then (assuming the CPU could run in a loop that tightly)?
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Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by NovemberWhiskey on Monday December 12, 2022 @04:31PM (#33960667)
No; because after the read, you need to precharge the row again (due to the design of dynamic RAM).

ref. https://en.wikipedia.org/wiki/Dynamic_random-access_memory#M...

The quoted "50 ns" DRAM has a read-cycle time of 84 ns.

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Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by kstrauser on Monday December 12, 2022 @04:56PM (#33960998)
Oh, interesting. I’ll read up more on that.
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