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Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by iamchp on Monday December 12, 2022 @10:34AM (#33955730)
This would benefit sequential access, but it'd either be disabled for random-access or pollute the caches with unused lines.

But in cases where sequential memory bandwidth is required, this is pretty cool! (But I assume Intel only, which would also be a bummer)

Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by fhars on Monday December 12, 2022 @11:39AM (#33956774)
RAM is the new tape...
Re:SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Speeds fo... by rektide on Monday December 12, 2022 @12:17PM (#33957308)
Somewhat ironic that we just reduced RAM channels from 64b down to 32b wide in DDR5 (but each DIMM has two channels). (newsflash if you missed it: desktop DDR5 is quad channel, but 32b, yes.)

SK Hynix: what if we increase the ram width to 64?