No way this can make economical sense. Every bit of wafer surface has much more value for transistors than improving thermal performance. The current state with a heat conductive plate atop of the silicon is certainly the best tradeoff, since thermal dissipation is the second most significant way to improve ship performance after actual transistors layout and conductivity.

Sure, for now. But it might create more stable ICs, or might even break some limitations due to heat runining up no the center of the CPU.. if a SoC can suddenly be x times as thick / have more layers, you can have shorter paths to different components. Which is faster again. The area of a wafer would remain the same, but I’m not sure about the economics of silicon wafers (thickness vs area). Less area mean less surface area for imperfections.

Without thermal performance, your transistors will have to stay mostly powered down ("dark silicon"). At some point, the tradeoff will go the other way.