Sounds like a fun project to do, I wonder if you could even implement it in full discrete logic and skip the FPGA

Is there an appreciable practical lower-bound in latency to that? I’ve never understood how-and-why electronic signals can propagate down a wire so gosh-darn quickly: the speed of sound is what I’d have intuitively expected, not 50-99% the speed of light ( https://en.wikipedia.org/wiki/Speed_of_electricity )

Essentially, energy is carried throughout a circuit by the electric field created by a voltage differential, not by electrons pushing other electrons like how sound is transmitted through a medium. So signals propagate on the same order of magnitude as the speed of light. I think this is a relatively intuitive explanation: https://www.youtube.com/watch?v=C7tQJ42nGno

I like the idea, but note that (1) and (2) can depend on what you’re used to. The fact that one doesn’t notice a handicap doesn’t mean that there isn’t room for improvement, given some conditioning.

I believe there are specific methods to negate these effects (something like going in a specific order with the values)

If would probably be interesting to randomize the latency for certain intervals with some kind of feedback mechanism to provide a blind study.

I remember when I got the iPhone X I was so used to higher latency that it felt like the iPhone was typing before I was. It was a very strange sensation until I got used to how quick it was.

If you ever end up doing this project, I find that sometimes it's hard to quantify if something is better when going in the normal-to-better direction, but it's always much easier to tell when something is worse when going in the normal-to-worse direction. So spend a few days or weeks getting totally acclimated to fast response times and then test if you can notice the difference with slow response times.