These days in x86 SoCs, DRAM is normally initialized by other cores smaller like the ME and PSP before the main core which would run the bios come up. For instance, apparently oxide's code doesn't have to bring up DRAM despite being the first code to run on the main cores.

On AMD Zen and later that is true, but on Intel the BIOS is still responsible for DRAM init (done via Intel's FSP)

The fact that DDR works at all is kinda black magic, every boot the memory controller does a training routine to understand the analog aspects of the specific ram and board in order to actually make it function at all. https://www.systemverilog.io/ddr4-initialization-and-calibra...

Edit: Reading the article is really cool, I just searched it as a reference but it is very in depth!

A lot of wifi/other wireless analog devices go through analogous training procedures. Things like timing and delays are pretty important to these types of systems and you don't have a clock edge to synchronize against like you do in wired protocols like SPI (though I imagine DDR initialization does have pins used for this or similar).

Yeah, DDR does have a synchronous clock. One of the points of calibration is making sure the signals are actually sampled correctly wrt to the clock signal since the bit times are so short even small differences of trace length matter. The length matching is just to get it in the ballpark that can be corrected with per pin delays.

Ironically perhaps, at bit times like these it's easier to not have a clock signal and simply perform clock recovery like PCIe does, but that comes with higher latency for the interface.

Probing (especially analog) is common throughout all discrete components. Baud rates are negotiated, clock speeds probed, handshakes made, etc.

The idea that DDR4/5 analog probing is “black magic” makes me think of a software engineer who’s had their first go at a hardware TRM.

Wow, what a fantastic resource. Extremely detailed while being concise, with links to other great explanations in the same site. Bookmarked

> which for modern DDR4 or DDR5 memory is a very complex and undocumented task

It’s most definitely documented; you simply don’t have access to said documents.

>The main task for any BIOS is to initialize the memory controller, which for modern DDR4 or DDR5 memory is a very complex and undocumented task, so it must be done usually by a binary firmware blob provided by Intel or AMD.

I don't question that binary blobs are distributed by Intel or AMD...

I also don't question that DDR5 memory is probably more complex (since it is newer, and newer technology is usually more complex) than DDR4, which is probably more complex than DDR3, etc., etc.

But, on a purely conceptual level, RAM is not all that complex... It's ridiculously simple. On a conceptual level, RAM is just a bunch of wires where most of those wires determine the address, some of those wires are for power, clock signal and ground, and some other of those wires move data back and forth to the CPU. Not complex at all!

The memory needs to be initialized? Well, maybe on startup it needs to be quickly calibrated/tested to make sure that a given RAM will work at a given frequency, but again, not rocket science!

If a memory controller requires a lot of complex initialization -- then maybe it isn't designed right?

A well-designed memory controller (if it were well designed) -- should abstract away details of what it does with the underlying memory such that it presents a single, simple, easy-to-understand, easy-to-initialize, unified, homogenous interface to memory.

In other words, no need for a lot of BIOS initialization code or black box binary blobs -- IF it is created correctly...

Somone doesn't like Intel or AMD black box binary blobs?

Well, people have (and I'm guessing more will, over time!) implemented their own memory controllers running on FPGA's...

Some of them are up to DDR4 capabilities...

https://github.com/oprecomp/DDR4_controller

https://www.google.com/search?q=open+source+ddr4+ip+core

But I'll let the statement "DDR5 memory is a very complex and undocumented task, so it must be done usually by a binary firmware blob provided by Intel or AMD." stand for now.

Yes, that's true as of 2022...

But will that continue to remain true?

?