Re:Chip Design Shifts as Fundamental Laws Run Out of Steam
by Rufbdbskrufb473 on Tuesday November 01, 2022 @03:30AM
(#33418083)
The missing thing that's critical for most multi-core performance use cases is memory bandwidth. Maybe not easy to summarize on a graph like this, but for any workload that can't fit within L1 cache, you're unlikely to get close to linear performance scaling with cores. Sometimes a single core can fully saturate the available memory bandwidth.
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