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A comment on RISC-V Public review for standard extensions Zc. Parent comment

Re:RISC-V Public review for standard extensions Zc by zozbot234 on Saturday October 15, 2022 @03:00AM (#33212477)
That's only the suggested overflow checking for a single operation. When you have multiple add/sub/mul/compare operations in a row, checking for actual overflow becomes quite non-trivial and is not something that can be done by the hardware. Floating point has no equivalent to this, which is why it makes sense to have overflow checking as part of the instruction.
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Re:RISC-V Public review for standard extensions Zc by throwaway81523 on Saturday October 15, 2022 @11:10AM (#33215509)
I don't understand what you are saying. An overflow in an intermediate result should signal an overflow unless you're relying on some special property of 2's complement arithmetic in which case you should be using specific datatypes to suppress the check. All I'm saying about floating point is that the presence of overflow checking in high performance FPU's falsifies (afaict) the claim that it's unfeasible to do the same thing for integers.
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Re:RISC-V Public review for standard extensions Zc by andrekandre on Saturday October 15, 2022 @07:40PM (#33219682) 

  > FPU's falsifies (afaict) the claim that it's unfeasible to do the same thing for integers.
was the argument that its unfeasible or that just not doing it is a net win?
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